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d a t a sh eet product speci?cation supersedes data of 1998 mar 17 2002 oct 02 integrated circuits 74lvc16373a; 74LVCH16373A 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state)
2002 oct 02 2 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A features 5 v tolerant inputs/outputs for interfacing with 5v logic wide supply voltage range from 1.2 to 3.6 v complies with jedec standard no. 8-1a cmos low power consumption multibyte tm flow-through standard pin-out architecture low inductance multiple power and ground pins for minimum noise and ground bounce direct interface with ttl levels all data inputs have bus hold (74LVCH16373A only) high-impedance when v cc =0v. description the 74lvc(h)16373a is a 16-bit d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus oriented applications. one latch enable (le) input and one output enable ( oe) are provided for each octal. inputs can be driven from either 3.3 or 5 v devices. in 3-state operation, outputs can handle 5 v. these features allow the use of these devices in a mixed 3.3 and 5 v environment. the 74lvc(h)16373a consists of 2 sections of eight d-type transparent latches with 3-state true outputs. when le is high, data at the dn inputs enter the latches. in this condition the latches are transparent, i.e., a latch output will change each time its corresponding d-input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when oe is low, the contents of the eight latches are available at the outputs. when oe is high, the outputs go to the high impedance off-state. operation of the oe input does not affect the state of the latches. the 74LVCH16373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns note 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i + s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacity in pf; v cc = supply voltage in volts; s (c l v cc 2 f o ) = sum of the outputs. symbol parameter conditions typical unit t phl /t plh propagation delay: c l = 50 pf; v cc = 3.3 v dn to qn 3.0 ns le to qn 3.4 ns c i input capacitance 5.0 pf c pd power dissipation per latch v cc = 3.3 v; note 1 26 pf
2002 oct 02 3 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A ordering information type number temperature range package pins package material code 74lvc16373adl - 40 to +85 c 48 tssop-48 plastic sot370-1 74lvc16373adgg - 40 to +85 c 48 tssop-48 plastic sot362-1 74LVCH16373Adl - 40 to +85 c 48 tssop-48 plastic sot370-1 74LVCH16373Adgg - 40 to +85 c 48 tssop-48 plastic sot362-1 pinning pin symbol description 11 oe output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 data inputs/outputs 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0 v) 7, 18, 31, 42 v cc supply voltage 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 data inputs/outputs 24 2 oe output enable input (active low) 25 2le latch enable input (active high) 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1le latch enable input (active high) handbook, halfpage mgu767 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 25 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1q0 1q1 gnd 1q2 1q3 v cc 1q4 1q5 gnd 1q6 1q7 2q0 2q1 gnd 2q2 2q3 v cc 2q4 2q5 gnd 2q6 2q7 2oe 1d0 1d1 gnd 1d2 1d3 v cc 1d4 1d5 gnd 1d6 1d7 2d0 2d1 gnd 2d2 2d3 v cc 2d4 2d5 gnd 2d6 2d7 2le 1oe 1le fig.1 pin configuration.
2002 oct 02 4 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A handbook, full pagewidth mgu769 2le d latch 9 q 2oe to 7 other channels le le 2q0 2d0 1le d latch 1 q 1oe to 7 other channels le le 1q0 1d0 fig.2 logic diagram. handbook, halfpage mgu768 1q 0 1q1 1le 2le 1q2 1q3 1q4 1q5 1q6 1q7 1oe 47 46 48 25 44 43 41 40 38 37 2 3 1 5 6 8 9 11 12 24 2q0 2q1 2q2 2q3 2q4 2q5 2q6 2q7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 2oe fig.3 logic symbol. handbook, halfpage 23 mgu770 37 12 11 9 8 6 5 47 46 44 43 41 40 38 1d7 1d0 1d1 1d2 1d3 1d4 1d5 1d6 2 3 1q7 1q6 1q5 1q4 1q3 1q2 1q0 1q1 26 22 20 19 17 16 36 35 33 32 30 29 27 2d5 2d0 2d1 2d2 2d3 2d4 13 14 2q5 2q4 2q3 2q2 2q1 2q0 24 25 2en 1oe 1 1en 1le 2oe 2le 48 c3 c4 3d 1 4d 2 2d7 2d6 2q7 2q6 fig.4 logic symbol (ieee/iec).
2002 oct 02 5 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A handbook, halfpage to internal circuit mgu771 v cc data input fig.5 bus hold circuit. function table per section of eight bits; note 1 note 1. h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; z = high-impedance off-state. operating modes input internal latches outputs q0 to q7 oe le dn enable and read register (transparent mode) l h l l l lhhhh latch and read register l l l l l llhhh latch register and disable outputs h l l l z hlhhz
2002 oct 02 6 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v); note 1. notes 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage output high or low state 0 v cc v output 3-state 0 5.5 v t amb operating ambient temperature in free-air - 40 +85 c t r ,t f input rise and fall times v cc = 1.2 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. typ. max. unit v cc supply voltage - 0.5 - +6.5 v i ik input diode current v i <0 -- 50 - v v i input voltage note 2 - 0.5 - +6.5 v i ok output diode current v o >v cc or v o <0 - 50 - v v o output voltage output high or low state; note 2 - 0.5 - v cc + 0.5 v output 3-state; note 2 - 0.5 - +6.5 v i o output source or sink current v o = 0 to v cc - 50 - ma i cc , i gnd v cc or gnd current - 100 - ma t stg storage temperature - 65 - +150 c p tot power dissipation per package so above 70 c derates linearly with 8 mw/k - 500 - mw ssop and tssop above 60 c derates linearly with 8 mw/k - 500 - mw
2002 oct 02 7 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A dc characteristics over recommended operating conditions; voltages are referenced to gnd (groun d=0v). notes 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. 2. for bus hold parts, the bus hold circuit is switched off when v i >v cc allowing 5.5 v on the input terminal. 3. valid for data inputs of bus hold parts (lvch16373a) only. 4. the specified sustaining current at the data input holds the input below the specified v i level. 5. the specified overdrive current at the data input forces the data input to the opposite logic input state. symbol parameter test conditions t amb ( c) unit other v cc (v) - 40 to +85 min. typ. (1) max. v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 12 ma 2.7 v cc - 0.5 -- v v i =v ih or v il ; i o = - 100 m a 3.0 v cc - 0.2 v cc - v v i =v ih or vil; i o = - 18 ma 3.0 v cc - 0.6 -- v v i =v ih or v il ; i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il ; i o = 12 ma 2.7 -- 0.40 v v i =v ih or v il ; i o = 100 m a 3.0 -- 0.20 v v i =v ih or v il ; i o = 24 ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd; note 2 3.6 - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd 3.6 - 0.1 5 m a i off power off leakage current v i or v o = 5.5 v 0 -- 10 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 3.6 - 0.1 20 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o = 0 2.7 to 3.6 - 5 500 m a i bhl bus hold low sustaining current v i = 0.8 v; notes 3 and 4 3.0 75 --m a i bhh bus hold high sustaining current v i = 2.0 v; notes 3 and 4 3.0 - 75 --m a i bhlo bus hold low overdrive current notes 3 and 5 3.6 500 --m a i bhho bus hold high overdrive current notes 3 and 5 3.6 - 500 --m a
2002 oct 02 8 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A ac characteristics gnd = 0 v; t r =t f = 2.5 ns; c l = 50 pf; r l = 500 w . note 1. typical values are measured at v cc = 3.3 v and t amb =25 c. symbol parameter waveforms t amb ( c) unit - 40 to +85 min. typ. max. v cc = 1.2 v t phl /t plh propagation delay dn to qn see figs 6 and 10 - 12 - ns t phl /t plh propagation delay le to qn see figs 7 and 10 - 14 - ns t pzh /t pzl 3-state output enable time oe to qn see figs 9 and 10 - 18 - ns t phz /t plz 3-state output enable time oe to qn see figs 9 and 10 - 11 - ns t w le pulse width high see fig.7 --- ns t su set-up time dn to le see fig.8 --- ns t h hold time dn to le see fig.8 --- ns v cc = 2.7 v t phl /t plh propagation delay dn to qn see figs 6 and 10 1.5 - 5.7 ns t phl /t plh propagation delay le to qn see figs 7 and 10 1.5 - 5.8 ns t pzh /t pzl 3-state output enable time oe to qn see figs 9 and 10 1.5 - 6.5 ns t phz /t plz 3-state output enable time oe to qn see figs 9 and 10 1.5 - 6.4 ns t w le pulse width high see fig.7 3 -- ns t su set-up time dn to le see fig.8 1.7 -- ns t h hold time dn to le see fig.8 1.2 -- ns v cc = 3.3 0.3 v; note1 t phl /t plh propagation delay dn to qn see figs 6 and 10 1.5 3.0 4.7 ns t phl /t plh propagation delay le to qn see figs 7 and 10 1.5 3.4 4.8 ns t pzh /t pzl 3-state output enable time oe to qn see figs 9 and 10 1.5 3.5 5.5 ns t phz /t plz 3-state output enable time oe to qn see figs 9 and 10 1.5 3.9 5.4 ns t w le pulse width high see fig.7 3 2.0 - ns t su set-up time dn to le see fig.8 +1.7 - 0.1 - ns t h hold time dn to le see fig.8 1.2 0.1 - ns
2002 oct 02 9 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A ac waveforms handbook, halfpage mgu772 dn input qn output t phl t plh gnd v i v m v m v m v oh v ol fig.6 input (dn) to output (qn) propagation delays. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. handbook, halfpage mgu773 le input qn output t phl t plh t w v m v m v oh v i gnd v ol v m v m v m fig.7 latch enable input (le) pulse width, and the latch enable input to output (qn) propagation delays. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load.
2002 oct 02 10 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A handbook, full pagewidth mgu774 t h t h t su t su v m v m v i gnd v i gnd le input dn input fig.8 data set-up and hold times for the dn input to the le input. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. the shaded areas indicate when the input is permitted to change for predictable performance. handbook, full pagewidth mgu775 t plz t phz outputs disabled outputs enabled v y v x outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v ol v oh v cc v m v m gnd gnd t pzl t pzh v m v m fig.9 3-state enable and disable times. v m = 1.5 v at v cc 3 2.7 v. v m = 0.5v cc at v cc < 2.7 v. v x =v ol + 0.3 v at v cc 3 2.7 v. v x =v ol + 0.1v cc at v cc < 2.7 v. v y =v oh - 0.3 v at v cc 3 2.7 v. v y =v oh - 0.1v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load.
2002 oct 02 11 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A handbook, full pagewidth open gnd 2 v cc v cc v in v out mgu776 d.u.t. c l r t r l 500 w r l 500 w pulse generator s1 fig.10 load circuitry for switching times. test s1 t plh /t phl open t plz /t pzl 2xv cc t phz /t pzh gnd v cc v i <2.7 v v cc 2.7 to 3.6 2.7 v definitions for test circuits: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2002 oct 02 12 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A package outlines unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 1.4 0.25 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 8 0 o o 0.18 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot370-1 95-02-04 99-12-27 (1) w m b p d h e e z e c v m a x a y 48 25 mo-118 24 1 q a a 1 a 2 l p q detail x l (a ) 3 pin 1 index 0 5 10 mm scale ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1 a max. 2.8
2002 oct 02 13 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 95-02-10 99-12-27 w m q a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 a max. 1.2 0 2.5 5 mm scale mo-153
2002 oct 02 14 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 oct 02 15 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 oct 02 16 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 oct 02 17 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A notes
2002 oct 02 18 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A notes
2002 oct 02 19 philips semiconductors product speci?cation 16-bit d-type transparent latch with 5 v tolerant inputs/outputs (3-state) 74lvc16373a; 74LVCH16373A notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/05/pp 20 date of release: 2002 oct 02 document order number: 9397 750 10037

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